Minimization of fractional wordlength on fixed-point conversion for high-level synthesis

Authors:
Nobuhiro Doi;Takashi Horiyama;Masaki Nakanishi;Shinji Kimura
Affiliations:
Waseda University, Kitakyushu;Kyoto University Kyoto;Nara Institute of Science and Technology, Nara;Waseda University, Kitakyushu
Venue:
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Year:
2004

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Abstract

In the hardware synthesis from high-level language such as C, bit length of variables is one of the key issues on the area and speed optimization. Usually, designers are required to specify the word length of each variable manually, and verify the correctness by the simulation on huge data. In this paper, we propose an optimization method of fractional wold length of floating-point variables in the floating to fixed-point conversion of variables. The amount of round-off erros are formulated with parameters and propagated via data flow graphs. The non-linear programming is used to solve the fractional wordlength minimization problem. The method does not require the simulation on huge data, and is very fast compared to ones based on the simulation. We have shown the effect on several programs.