Automatic floating-point to fixed-point conversion for DSP code generation
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Minimization of fractional wordlength on fixed-point conversion for high-level synthesis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Lightweight floating-point arithmetic: case study of inverse discrete cosine transform
EURASIP Journal on Applied Signal Processing
Floating-to-fixed-point conversion for digital signal processors
EURASIP Journal on Applied Signal Processing
Proceedings of the 45th annual Design Automation Conference
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis
Journal of Signal Processing Systems
| Hi-index | 0.00 |
Complete fixed-point error models that include the coefficient quantization are derived for two popular 8×8 two-dimensional (2-D) IDCT architectures; one is based on distributed arithmetic, and the other is the multiplier-adder chain. The error models are evaluated in the integer domain to accurately measure the effects of rounding. The analysis results show that the overall mean-square error performance (OMSE) is the most critical condition for meeting the IEEE specification (IEEE Std. 1180-1990) when the rounding scheme is employed. On the other hand, the mean error effects (OME and PME) are dominant for truncation. Finally, the analysis results are compared with those of bit-accurate simulation