Design and FPGA implementation an accurate real time 3x4 MIMO channel emulator

  • Authors:
  • Omar A. Nasr;Babak Daneshrad

  • Affiliations:
  • -;-

  • Venue:
  • Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
  • Year:
  • 2009

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Abstract

The design and implementation of an accurate and low complexity MIMO channel emulator is presented in this paper. A mathematical analysis is used to verify the accuracy of the emulator over a wide range of SNRs (0 - 35 dBs). The complexity of the emulator is reduced by preprocessing of the channels and hardware/software partitioning. All 802.11n channels models can be emulated on our platform. A 3×4 10MHz version of the emulator is successfully running on a Virtex-II XC2V6000-4 FPGA. A 20MHz version was synthesized and simulated on an XC2V6000-6 FPGA.