A Gaussian Noise Generator for Hardware-Based Simulations
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Hardware simulation of channel codes offers thepotential of improving code evaluation speed by ordersof magnitude over workstation- or PC-based simulation.We describe a hardware-based Gaussian noisegenerator used as a key component in a hardware simulationsystem, for exploring channel code behavior atvery low bit error rates (BERs) in the range of 10-9to 10-10. The main novelty is the design and use ofnon-uniform piecewise linear approximations in computingtrigonometric and logarithmic functions. Theparameters of the approximation are chosen carefullyto enable rapid computation of coefficients from theinputs, while still retaining extremely high fidelity tothe modelled functions. The output of the noise generatoraccurately models a true Gaussian PDF evenat very high \sigma values. Its properties are explored using:(a) several different statistical tests, including thechi-square test and the Kolmogorov-Smirnov test, and(b) an application for decoding of low density paritycheck (LDPC) codes. An implementation at 133MHzon a Xilinx Virtex-II XC2V4000-6 FPGA produces 133million samples per second, which is 40 times fasterthan a 2.13GHz PC; another implementation on a XilinxSpartan-IIE XC2S300E-7 FPGA at 62MHz is capableof a 20 times speedup. The performance can beimproved by exploiting parallelism: an XC2V4000-6FPGA with three parallel instances of the noise generatorat 126MHz can run 100 times faster than a2.13GHz PC. We illustrate the deterioration of clockspeed with the increase in the number of instances.