High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
A New Method for Optical Vector-Matrix Multiplier
ICECT '09 Proceedings of the 2009 International Conference on Electronic Computer Technology
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This paper implements Optical Vector-Matrix Multiplication (OVMM) completely in parallel on a novel optical computing architecture, Ternary Optical Computer (TOC), by use of the Modified Signed-Digit (MSD) number system. For high efficiency, partial products (PPs) are generated in parallel and the vector inner products (VIPs) are produced by a binary-tree algorithm, and then the OVMM is implemented. The experimental result validates the feasibility and correctness of VMM on TOC. In this system, it is not necessary to gauge light intensities, but judge whether there is light during decoding.