High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
Modern control engineering (3rd ed.)
Modern control engineering (3rd ed.)
Phase-Locked Loops for Wireless Communications: Digital and Analog Implementation
Phase-Locked Loops for Wireless Communications: Digital and Analog Implementation
4.4: Application of VHDL to Software Radio Technology
IVC-VIUF '98 Proceedings of the International Verilog HDL Conference and VHDL International Users Forum
Linear Systems
Digital Signal Processing (4th Edition)
Digital Signal Processing (4th Edition)
Maximum likelihood carrier phase synchronization in FPGA-based software defined radios
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
High-speed CMOS analog-to-digital converter for front-end receiver applications
Proceedings of the 20th annual conference on Integrated circuits and systems design
All-digital PLL using bulk-controlled varactor and pulse-based digitally controlled oscillator
Analog Integrated Circuits and Signal Processing
International Journal of Reconfigurable Computing
Hi-index | 0.00 |
Software-defined radio (SDR) is a revolution in radio design due to the ability to create radios that can self-adapt on the fly. In SDR devices, all of the signal processing is implemented in the digital domain, mainly on DSP blocks or by DSP software. By simply downloading a new program, a SDR device is able to interoperate with different wireless protocols, incorporate new services, and upgrade to new standards. Therefore, massively parallel signal processing at higher frequencies are needed to implement a realistic SDR. Thus, FPGAs have been used extensively for implementing essential functions in SDR architectures at lower frequencies. In this paper, we explore the design of a digital FM receiver using the approach of an All-Digital Phase Locked-Loop (ADPLL). The circuit is designed in VHDL, then synthesized and simulated using LeonardoSpectrum Level 3 and ModelSim SE 6, respectively. It operates at a frequency up to 150 MHz and occupies the area of roughly 15 K logic gates.