Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Fault-tolerant computing: theory and techniques; vol. 1
Coding techniques in fault-tolerant, self-checking, and fail-safe circuits
Fault-tolerant computing: theory and techniques; vol. 1
Introduction to VLSI Systems
Concurrent Error Detection in Multiply and Divide Arrays
IEEE Transactions on Computers
Concurrent Error Detection in ALU's by Recomputing with Shifted Operands
IEEE Transactions on Computers
Fault Detection Capabilities of Alternating Logic
IEEE Transactions on Computers
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Concurrent off-phase built-in self-test permits the operation of built-in self-test hardware designed for off-line testing concurrently with normal system operation. It takes advantage of the logic dormancy characteristic of designs which use two phase clocking. This method provides on-line detection for permanent faults and can be used in conjunction with a time redundant concurrent test methods to detect transient and intermittent as well as permanent faults. Also, the method provides guaranteed self-test for self-checking circuits. Concurrent off-phase BIST requires duplication of storage elements but otherwise makes use of BIST hardware employed for nonconcurrent, off-line testing. Also, there may be an associated time penalty which, for an example CMOS technology with a symmetric phase clock period of 50 ns, is estimated to be an 11.6% increase in the clock period.