Error correction by alternate-date retry
Error correction by alternate-date retry
Implementation of an Experimental Fault-Tolerant Memory System
IEEE Transactions on Computers
An on-line testable UART implemented using IFIS
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Concurrent Error Detection in Multiply and Divide Arrays
IEEE Transactions on Computers
Algorithm-Based Fault Tolerance for Matrix Operations
IEEE Transactions on Computers
Concurrent Error Detection in ALU's by Recomputing with Shifted Operands
IEEE Transactions on Computers
Pay-As-You-Go: low-overhead hard-error correction for phase change memories
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
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A new technique for low-cost error correction is the alternate-data retry (ADR). Like a conventional retry, an ADR is a re-execution of an operation that initially fails to produce an error-free result. Unlike a conventional retry, an ADR uses an alternate representation of the initial data. The choice of the alternate data representation and the design of the processing circuits combine to insure that even an error due to a permanent fault is not repeated during retry. Error correction is provided at a hardware cost comparable to that of a conventional retry capability.