Deterministic Pattern Generation for Weighted Random Pattern Testing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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A method for weighted pseudorandom test generation based on a deterministic test set is described. The main advantages of the method described over existing methods are: (1) only three easily generated weights (0, 0.5 and 1) are used, (2) a minimum number of shift register cells is used, thus leading to minimal hardware for built-in-test applications, and (3) the weights are selected to allow the same coverage of target faults attained by the deterministic test set to be attained by weighted random patterns. The weights are computed by walking through the range of test generation approaches from pure random at one extreme to deterministic at the other extreme, dynamically selecting the weight assignments to correspond to the remaining faults at every stage. Hardware suitable for the generation of random patterns under the proposed method is described. The method is suitable for both combinational and sequential circuits. Experimental results are provided for ISCAS-85 and MCNC benchmark circuits