Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of FIRE: a case study
DAC '97 Proceedings of the 34th annual Design Automation Conference
Formal verification in a commercial setting
DAC '97 Proceedings of the 34th annual Design Automation Conference
Symbolic Model Checking
On-the-Fly Model Checking of RCTL Formulas
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Prioritized Traversal: Efficient Reachability Analysis for Verification and Falsification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Efficient Fixpoint Computation for Invariant Checking
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
An Algorithmic Approach to Design Exploration
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
CTL Model-Checking with Graded Quantifiers
ATVA '08 Proceedings of the 6th International Symposium on Automated Technology for Verification and Analysis
Explaining Counterexamples Using Causality
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Graded-CTL: Satisfiability and Symbolic Model Checking
ICFEM '09 Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Enhancing Test Coverage by Back-tracing Model-checker Counterexamples
Electronic Notes in Theoretical Computer Science (ENTCS)
A framework for counterexample generation and exploration
FASE'05 Proceedings of the 8th international conference, held as part of the joint European Conference on Theory and Practice of Software conference on Fundamental Approaches to Software Engineering
Explaining counterexamples using causality
Formal Methods in System Design
Fundamenta Informaticae - Advances in Computational Logic (CIL C08)
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In this paper, we emphasize the importance of efficient debugging in formal verification and present capabilities that we have developed in order to augment debugging in Intel's Formal Verification Environment. We have given the name the "counter-example wizard" to the bundle of capabilities that we have developed to address the needs of the verification engineer in context of counter-example diagnosis and rectification. The novel features of the counterexample wizard are the "multi-value counter-example annotation," "multiple root cause detection," and "constraint-based debugging" mechanisms. Our experience with the verification of real-life Intel designs shows that these capabilities complement one another and can considerably help the verification engineer diagnose and fix a reported failure. We use real-life verification cases to illustrate how our system solution can significantly reduce the time spent in the loop of model checking, specification and design modification.