Efficient coverage of parallel and hierarchical stateflow models for test case generation

  • Authors:

  • Manoranjan Satpathy;Anand Yeolekar;Prakash Peranandam;S. Ramesh

  • Affiliations:

  • India Science Laboratory, General Motors Global R&D, International Tech Park, Bangalore 560 066, India;India Science Laboratory, General Motors Global R&D, International Tech Park, Bangalore 560 066, India;India Science Laboratory, General Motors Global R&D, International Tech Park, Bangalore 560 066, India;India Science Laboratory, General Motors Global R&D, International Tech Park, Bangalore 560 066, India

  • Venue:
  • Software Testing, Verification & Reliability
  • Year:
  • 2012

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Abstract

This paper is concerned with test case generation from Simulink/Stateflow (SL/SF) models with a focus on coverage of SF model elements. Coverage of the SF component in a model is a difficult task because of two primary reasons: (i) the SF component itself may lie deep in the SL/SF model in which case, inputs have to pass through a complex chain of SL blocks to reach the SF block and (ii) nonlinear constraints in the model are difficult to solve using constraint solvers. Hierarchy and parallelism in the SF model add further complexity to the problem. The existing approaches flatten such SF elements, and generate test cases from the flattened finite state machines. Handling of issues (i) and (ii) has already been discussed in earlier research. In this paper, we present a method of covering SF components, which does not require to flatten any hierarchy or parallelism in the components. This not only makes the test case generation problem efficient but also addresses the problem of scalability. We have implemented this method and performed a number of medium-sized case studies. The results show improved performance over the results obtained by some commercial tools. Copyright © 2011 John Wiley & Sons, Ltd.