Hardware/software co-simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Software timing analysis using HW/SW cosimulation and instruction set simulator
Proceedings of the 6th international workshop on Hardware/software codesign
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
DART: directed automated random testing
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
CUTE: a concolic unit testing engine for C
Proceedings of the 10th European software engineering conference held jointly with 13th ACM SIGSOFT international symposium on Foundations of software engineering
Optimal On-Line Scheduling of Multiple Control Tasks: A Case Study
ECRTS '06 Proceedings of the 18th Euromicro Conference on Real-Time Systems
Resource Management for Control Tasks Based on the Transient Dynamics of Closed-Loop Systems
ECRTS '06 Proceedings of the 18th Euromicro Conference on Real-Time Systems
ICSE '07 Proceedings of the 29th international conference on Software Engineering
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
AutoMOTGen: Automatic Model Oriented Test Generator for Embedded Control Systems
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Symbolic analysis for improving simulation coverage of Simulink/Stateflow models
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Randomized directed testing (REDIRECT) for Simulink/Stateflow models
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Task Scheduling for Control Oriented Requirements for Cyber-Physical Systems
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Delay-Aware Period Assignment in Control Systems
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
The theory of deadlock avoidance via discrete control
Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
An approach to reverse engineering of C programs to simulink models with conformance testing
Proceedings of the 2nd India software engineering conference
Generating and Analyzing Symbolic Traces of Simulink/Stateflow Models
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
From MC/DC to RC/DC: formalization and analysis of control-flow testing criteria
Formal methods and testing
Reducing Delay Jitter of Real-Time Control Tasks through Adaptive Deadline Adjustments
ECRTS '10 Proceedings of the 2010 22nd Euromicro Conference on Real-Time Systems
Modeling and simulation of TDL applications
MBEERTS'07 Proceedings of the 2007 International Dagstuhl conference on Model-based engineering of embedded real-time systems
Co-design of cyber-physical systems via controllers with flexible delay constraints
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Game time: a toolkit for timing analysis of software
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Migration of legacy software towards correct-by-construction timing behavior
FOCS'10 Proceedings of the 16th Monterey conference on Foundations of computer software: modeling, development, and verification of adaptive systems
Constraint-driven synthesis and tool-support for FlexRay-based automotive control systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An Analysis and Survey of the Development of Mutation Testing
IEEE Transactions on Software Engineering
Efficient coverage of parallel and hierarchical stateflow models for test case generation
Software Testing, Verification & Reliability
Journal of Control Science and Engineering - Special issue on Embedded-Model-Based Control
Analysis and testing of matlab simulink models: a systematic mapping study
Proceedings of the 2013 International Workshop on Joining AcadeMiA and Industry Contributions to testing Automation
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Automotive architectures today consist of up to 100 electronic control units (ECUs) that communicate via one or more FlexRay and CAN buses. Multiple control applications - like cruise control, brake control, etc. are specified as Simulink/Stateflow models, from which code is generated and mapped onto the different ECUs. In addition, scheduling policies and parameters, both for the ECUs and the buses, need to be specified. Code generation/optimization from the Simulink/Stateflow models, task partitioning and mapping decisions, as well as the parameters chosen for the schedulers all of these impact the execution times and timing behaviour of the control tasks and control messages. These in turn affect control performance, such as stability and steady-/transient-state behaviour. This paper discusses different aspects of this multi-layered design flow and the associated research challenges. The emphasis is on model-based code generation, analysis, testing and verification of control software for automotive architectures, as well as on architecture or platform configuration to ensure that the required control performance requirements are satisfied.