A mathematical model for the verification of systolic networks
SIAM Journal on Computing
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
Introduction to VLSI Systems
Real-Time Computation by n-Dimensional Iterative Arrays of Finite-State Machines
IEEE Transactions on Computers
Computer
Optimizing synchronous systems
SFCS '81 Proceedings of the 22nd Annual Symposium on Foundations of Computer Science
Real-time language recognition by one-dimensional cellular automata
Journal of Computer and System Sciences
Parallel parsing on a one-way array of finite-state machines
IEEE Transactions on Computers
An improved systematic method for constructing systolic arrays from algorithms
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
On the power of one-way communication
Journal of the ACM (JACM)
String Editing on a One-Way Linear Array of Finite-State Machines
IEEE Transactions on Computers
On Mapping Systolic Algorithms onto the Hypercube
IEEE Transactions on Parallel and Distributed Systems
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We present a tool that is useful in the design and analysis of systolic systems. Specifically, we give characterizations of systolic arrays in terms of (single processor) sequential machines which are easier to program and to analyze. We give several examples to illustrate the utility of the design tool. In particular, we show how systolic designs for such problems as integer bitwise multiplication, dynamic programming, and language recognition can easily be derived using the characterizations. We also present some new results concerning the properties and computational power of systolic arrays which can be obtained using the characterizations.