FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing

Authors:
Krzysztof Kępa;Fearghal Morgan;Krzysztof Kościuszkiewicz;Lars Braun;Michael Hübner;Jürgen Becker
Affiliations:
Bio-Inspired Electronics and Reconfigurable Computing Group, Dept.of Electronic Engineering, National University of Ireland, Galway, Ireland;Bio-Inspired Electronics and Reconfigurable Computing Group, Dept.of Electronic Engineering, National University of Ireland, Galway, Ireland;Bio-Inspired Electronics and Reconfigurable Computing Group, Dept.of Electronic Engineering, National University of Ireland, Galway, Ireland;Institut für Technik der Informationsverarbeitung (ITIV), Universität Karlsruhe (TH), Germany;Institut für Technik der Informationsverarbeitung (ITIV), Universität Karlsruhe (TH), Germany;Institut für Technik der Informationsverarbeitung (ITIV), Universität Karlsruhe (TH), Germany
Venue:
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Year:
2009

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Abstract

The growth of the reconfigurable systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Those targeting reconfigurable design analysis and manipulation require low-level design tools for bitstream debugging and IP core design assurance. While tools for low-level analy sis of design netlists do exist there is a need for a low-level, open-source, extended tool support. This paper reports a Field Programmable Gate Array (FPGA) Analysis Tool (FAT) being a versatile, modular and open-source tools framework for low-level analysis and verification of FPGA designs. The analysis performed by FAT is based on available Xilinx FPGA device specification data. FAT provides a set of standalone, high-level Application Programming Interfaces (APIs) abstracting the Xilinx FPGA fabric, the placed and routed design netlist and the related bitstream. The operation of FAT is governed by "recipe" scripts. A lightweight graphic front-end allows visualisation of the design within the FPGA fabric. The paper illustrates the application of FAT for bit-pattern analysis of the Virtex-II Pro inter-tile routing and verification of the spatial isolation between designs.