Aegis: A Single-Chip Secure Processor

  • Authors:
  • G. Edward Suh;Charles W. O'Donnell;Srinivas Devadas

  • Affiliations:
  • Cornell University;Massachusetts Institute of Technology;Massachusetts Institute of Technology

  • Venue:
  • IEEE Design & Test
  • Year:
  • 2007

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Abstract

This article presents the Aegis secure processor architecture, which enables physically secure computing platforms with a main processor as the only trusted component. The Aegis architecture ensures private and authentic program execution even in the face of physical attacks, using two new security primitives. First, physical unclonable functions (PUFs) generate cryptographic keys in a highly secure yet inexpensive manner, exploiting random manufacturing variations. Second, off-chip memory protection mechanisms ensure the integrity and privacy of off-chip memory. Aegis, with its new protection mechanisms, has been implemented on an FPGA, and is fully functional. The authors briefly assess the cost of the security mechanisms in the Aegis processor and show that it is reasonable.