Silicon physical random functions
Proceedings of the 9th ACM conference on Computer and communications security
Controlled Physical Random Functions
ACSAC '02 Proceedings of the 18th Annual Computer Security Applications Conference
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Proceedings of the 44th annual Design Automation Conference
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IEEE Design & Test
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Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
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CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
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Proceedings of the 1st ACM workshop on Virtual machine security
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ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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IEEE Transactions on Computers
ACM SIGDA Newsletter
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SOFSEM'11 Proceedings of the 37th international conference on Current trends in theory and practice of computer science
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CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
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Cryptography and Security
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This paper introduces a novel technique for extracting the unique timing signatures of the FPGA configurable logic blocks in a digital form over the space of possible challenges. A new class of physical unclonable functions that enables inputs challenges such as timing, digital, and placement challenges can be built upon the delay signatures. We introduce a suite of new authentication protocols that take into account non-triviality of bitstream reverse-engineering in addition to the FPGA's unprecedented speed in responding to challenges. Our technique is secure against various attacks and robust to fluctuations in operational conditions. Proof of concept implementation of the signature extraction and evaluations of the proposed methods are demonstrated on Xilinx Virtex 5 FPGAs. Experimental results demonstrate practicality of the proposed techniques.