A security approach for off-chip memory in embedded microprocessor systems

  • Authors:

  • Romain Vaslin;Guy Gogniat;Jean-Philippe Diguet;Eduardo Wanderley;Russell Tessier;Wayne Burleson

  • Affiliations:

  • European University of Brittany, CNRS, UMR 3192 - Lab-STICC, Centre de recherche, BP 92116, 56321 Lorient, France;European University of Brittany, CNRS, UMR 3192 - Lab-STICC, Centre de recherche, BP 92116, 56321 Lorient, France;European University of Brittany, CNRS, UMR 3192 - Lab-STICC, Centre de recherche, BP 92116, 56321 Lorient, France;CEFET-RN, Natal-RN, CEP 59015-000, Brazil;University of Massachusetts, Department of Electrical and Computer Engineering, Amherst, MA 01003, USA;University of Massachusetts, Department of Electrical and Computer Engineering, Amherst, MA 01003, USA

  • Venue:
  • Microprocessors & Microsystems
  • Year:
  • 2009

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Abstract

This paper describes a complete off-chip memory security solution for embedded systems. Our security core is based on a one-time pad (OTP) encryption circuit and a CRC-based integrity checking module. These modules safeguard external memory used by embedded processors against a series of well-known attacks, including replay attacks, spoofing attacks and relocation attacks. Our implementation limits on-chip memory space overhead to less than 33% versus memory used by a standard microprocessor and reduces memory latency achieved by previous approaches by at least half. The performance loss for software execution with our solution is only 10% compared with a non-protected implementation. An FPGA prototype of our security core has been completed to validate our findings.