Securing embedded programmable gate arrays in secure circuits

Authors:
Nicolas Valette;Lionel Torres;Gilles Sassatelli;Frédéric Bancel
Affiliations:
STMicroelectronics, Rousset Cedex, France and LIRMM, UMR, Microelectronics Department, Montpellier Cedex 5, France;LIRMM, UMR, Microelectronics Department, Montpellier Cedex 5, France;LIRMM, UMR, Microelectronics Department, Montpellier Cedex 5, France;STMicroelectronics, Rousset Cedex, France
Venue:
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Year:
2006

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Abstract

The purpose of this article is to propose a survey of possible approaches for implementing embedded reconfigurable gate arrays into secure circuits. A standard secure interfacing architecture is proposed and motivations justifying such an approach are discussed. This paper also lists all features offered by FPGA vendors (Field Programmable Gate Array) aiming at securing those circuits according to different concerns. This article emphasizes on configuration memory programming which is probably the weakest point of using programmable devices on a secure context.