Computing the Hough Transform on a Scan Line Array Processor (Image Processing)
IEEE Transactions on Pattern Analysis and Machine Intelligence
A binary Hough transform and its efficient implementation in a systolic array architecture
Pattern Recognition Letters
Fast Hough transform on a mesh connected processor array
Information Processing Letters
A hierarchical approach to line extraction based on the Hough transform
Computer Vision, Graphics, and Image Processing
A parallel Hough transform algorithm for nonuniform images
Pattern Recognition Letters
Pipelined implementation of the multiresolution Hough transform in a pyramid multiprocessor
Pattern Recognition Letters
Cordic based parallel/pipelined architecture for the Hough transform
Journal of VLSI Signal Processing Systems
A survey of CORDIC algorithms for FPGA based computers
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A real-time hardware implementation of the Hough transform
Journal of Systems Architecture: the EUROMICRO Journal
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Use of the Hough transformation to detect lines and curves in pictures
Communications of the ACM
Hough transform algorithm for FPGA implementation
Signal Processing - Special section on information theoretic aspects of digital watermarking
Digital Image Processing
Computer Vision
High-speed parameterisable Hough transform using reconfigurable hardware
VIP '01 Proceedings of the Pan-Sydney area workshop on Visual information processing - Volume 11
A High Speed Hough Transform Using CORDIC
A High Speed Hough Transform Using CORDIC
Design and Integration of Parallel Hough-Transform Chips for High-speed Line Detection
ICPADS '05 Proceedings of the 11th International Conference on Parallel and Distributed Systems - Workshops - Volume 02
Finding Picture Edges Through Collinearity of Feature Points
IEEE Transactions on Computers
Resource-efficient FPGA architecture and implementation of hough transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keeping the vehicle on the road: A survey on on-road lane detection systems
ACM Computing Surveys (CSUR)
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Accelerating Hough transform in hardware has been of interest due its popularity in real-time capable image processing applications. In most existing linear Hough transform architectures, an edge m × m map is serially read for processing, resulting in a total computation time of at least m2 cycles. In this paper, we propose a novel parallel Hough transform computation method called the Additive Hough transform (AHT), wherein the image is divided using a k × k grid to reduce the total computation time by a factor of k2. We have also proposed an efficient implementation of the AHT consisting of a look-up table (LUT) and two-operand adder arrays for every angle. Techniques to condense the LUT size have also been proposed to further reduce area utilization by as much as 50%. Our investigations based on employing an 8 × 8 grid shows a 1000 × speedup compared to existing architectures for a range of image sizes. Area-time trade-off analysis has been presented to demonstrate that the area-time product of the proposed AHT-based implementation is at least 43% lower than other implementations reported in the literature. We have also included and characterized a hierarchical addition step in order to generate a global accumulation space equivalent to that of the conventional HT. It is shown that the proposed implementation with the hierarchical addition step remains superior to other methods in terms of both performance and area-time product metrics. Finally, we show that the proposed solution is equally efficient when applied on rectangular images.