Exploiting inherent parallelisms for accelerating linear Hough transform
IEEE Transactions on Image Processing
Gradient angle histograms for efficient linear Hough transform
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
Resource-efficient FPGA architecture and implementation of hough transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Line detection is often needed in computer vision applications. The Hough transform processing of image data for line detection is robust but time-consuming. With the use of multiple processors, the processing time for Hough transform can be much reduced. In our research, we design an array processor for line-detection based on Hough transform that performs the line-parameter calculation and accumulation for different angles in parallel. Such an array processor together with its parallel peak extraction circuits have been implemented on a single chip. Based on the TSMC 0.35µm CMOS technology, the fabricated chip (with 10 processors) can be run successfully up to the clock rate of 50MHz. This paper presents the SOC design that can be extended to the integration of multiple chips to form a faster system with more parallel processors.