A Real-Time Processor for the Hough Transform
IEEE Transactions on Pattern Analysis and Machine Intelligence
Computing the Hough Transform on a Scan Line Array Processor (Image Processing)
IEEE Transactions on Pattern Analysis and Machine Intelligence
Pipelined implementation of the multiresolution Hough transform in a pyramid multiprocessor
Pattern Recognition Letters
Cordic based parallel/pipelined architecture for the Hough transform
Journal of VLSI Signal Processing Systems
A survey of CORDIC algorithms for FPGA based computers
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Use of the Hough transformation to detect lines and curves in pictures
Communications of the ACM
Hough transform algorithm for FPGA implementation
Signal Processing - Special section on information theoretic aspects of digital watermarking
High-speed parameterisable Hough transform using reconfigurable hardware
VIP '01 Proceedings of the Pan-Sydney area workshop on Visual information processing - Volume 11
A High Speed Hough Transform Using CORDIC
A High Speed Hough Transform Using CORDIC
ICIAP '03 Proceedings of the 12th International Conference on Image Analysis and Processing
Design and Integration of Parallel Hough-Transform Chips for High-speed Line Detection
ICPADS '05 Proceedings of the 11th International Conference on Parallel and Distributed Systems - Workshops - Volume 02
Data Compression: The Complete Reference
Data Compression: The Complete Reference
Real-time line detection through an improved Hough transform voting scheme
Pattern Recognition
Finding Picture Edges Through Collinearity of Feature Points
IEEE Transactions on Computers
ACM SIGARCH Computer Architecture News
Pattern Recognition Letters
On line mode incremental Hough transform implementation on Xilinx Fpga's
SSIP'08 Proceedings of the 8th conference on Signal, Speech and image processing
A Swift and Memory Efficient Hough Transform for Systems with Limited Fast Memory
ICIAR '09 Proceedings of the 6th International Conference on Image Analysis and Recognition
Exploiting inherent parallelisms for accelerating linear Hough transform
IEEE Transactions on Image Processing
Real-time FPGA implementation of Hough Transform using gradient and CORDIC algorithm
Image and Vision Computing
FPGA Implementation of the Generalized Hough Transform
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
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Hough transform is widely used for detecting straight lines in an image, but it involves huge computations. For embedded application, field-programmable gate arrays are one of the most used hardware accelerators to achieve real-time implementation of Hough transform. In this paper, we present a resource-efficient architecture and implementation of Hough transform on an FPGA. The incrementing property of Hough transform is described and used to reduce the resource requirement. In order to facilitate parallelism, we divide the image into blocks and apply the incrementing property to pixels within a block and between blocks. Moreover, the locality of Hough transform is analyzed to reduce the memory access. The proposed architecture is implement on an Altera EP2S180F1508C3 device and can operate at a maximum frequency of 200 MHz. It could compute the Hough transform of 512 × 512 test images with 180 orientations in 2.07-3.16 ms without using many FPGA resources (i.e., one could achieve the performance by adopting a low-cost low-end FPGA).