Design and analysis of matching circuit architectures for a closest match lookup

Authors:
Kieran McLaughlin;Friederich Kupzog;Holger Blume;Sakir Sezer;Tobias Noll;John McCanny
Affiliations:
The Institute of Electronics, Communications and Information Technology at QUB;The Institute of Electrical Engineering and Computer Systems at RWTH Aachen University;The Institute of Electrical Engineering and Computer Systems at RWTH Aachen University;The Institute of Electronics, Communications and Information Technology at QUB;The Institute of Electrical Engineering and Computer Systems at RWTH Aachen University;The Institute of Electronics, Communications and Information Technology at QUB
Venue:
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Year:
2006

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Abstract

This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results.