Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
Novel architectures for efficient (m, n) parallel counters
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Emerging nanocircuit paradigm: Graphene-based electronics for nanoscale computing
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
Single-walled carbon nanotube electronics
IEEE Transactions on Nanotechnology
Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing
IEEE Transactions on Nanotechnology
Alternate State Variables for Emerging Nanoelectronic Devices
IEEE Transactions on Nanotechnology
Heterogeneous Two-Level Logic and Its Density and Fault Tolerance Implications in Nanoscale Fabrics
IEEE Transactions on Nanotechnology
Regular 2D NASIC-based architecture and design space exploration
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Spin wave functions nanofabric update
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Hybrid Graphene Nanoribbon-CMOS tunneling volatile memory fabric
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
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This paper argues for alternate state variables and new types of sophisticated devices that implement more functionality in one computational step than typical devices based on simple switches. Elementary excitations in solids enabling wave interactions are possible initial candidates to create such new devices. The paper focuses on magnon-based spin-wave-logic functions (SPWF) and presents high fan-in majority, weighted high fan-in majority, and frequency-multiplexed weighted high fan-in majority devices as initial SPWFs. Experiments proving feasibility are also shown. Benefits vs. scaled CMOS are quantified. Results show that for 128 or larger inputs even a 2.5μm SPWF carry-look-ahead adder implementation is faster than the 45nm CMOS version. The 45nm SPWF adder is expected to be significantly faster across the whole range of input widths. In particular, the 45nm SPWF CLA adder is estimated to be at least 77X faster than CMOS version for input widths equal to or greater than 1024. A second example of a counter circuit is presented to illustrate the considerable reduction in complexity possible vs. CMOS.