Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
A global approach to improve conditional hardware reuse in high-level synthesis
Journal of Systems Architecture: the EUROMICRO Journal
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration
IEEE Transactions on Computers
RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability
RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability
Advanced FPGA Design: Architecture, Implementation, and Optimization
Advanced FPGA Design: Architecture, Implementation, and Optimization
Recurrence-aware instruction set selection for extensible embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Resource Sharing in Custom Instruction Set Extensions
SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Design-space exploration of resource-sharing solutions for custom instruction set extensions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Computer Arithmetic: Algorithms and Hardware Designs
Computer Arithmetic: Algorithms and Hardware Designs
Efficient datapath merging for partially reconfigurable architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-) configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.