A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems

  • Authors:

  • Xingjun Wu; Hongyi Chen; Yihe Sun; Weixin Gai

  • Affiliations:

  • Institute of Microelectronics, Tsinghua University, Beijing 100084, People's Republic of China;Institute of Microelectronics, Tsinghua University, Beijing 100084, People's Republic of China;Institute of Microelectronics, Tsinghua University, Beijing 100084, People's Republic of China;Institute of Microelectronics, Tsinghua University, Beijing 100084, People's Republic of China

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2002

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Abstract

In this paper, a fully-pipeline linear systolic array based on adjusted Montgomery's algorithm is presented to perform modular multiplication at extremely high speed. The processing element (PE) consists of only 4 full-adders and 14 flip-flops. Three-stage internal pipelined PE results in a very short critical path with only a one-bit full-adder delay. Thus, it can run at a very high cycle rate. The total execution time for an n-bit modular multiplication is 2n + 11 cycles with only (n/2 + 2) PEs. A modular exponentiation based on it takes (3n + 16.5)n cycles in average. Compared with most published VLSI modular multipliers, the hardware complexity is greatly reduced while keeping very high throughput. Therefore it is a good candidate of the arithmetic units used in the many public-key crypto-systems, e.g. RSA, Elliptic Curve and so on, especially for the embedded applications concerning information security.