VLSI array processors
Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
Comparison of three modular reduction functions
CRYPTO '93 Proceedings of the 13th annual international cryptology conference on Advances in cryptology
Principles of digital design
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Linear systolic multiplier/squarer for fast exponentiation
Information Processing Letters
Systolic Modular Multiplication
IEEE Transactions on Computers
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A new processing element (PE) structure and serial-in-serial-out systolic multiplier are proposed for the efficient implementation of Montgomery's modular multiplication algorithm in RSA cryptosystem. By reorganizing and analyzing the recursive equation of Montgomery algorithm at the Boolean operator level, the critical path delay of the proposed PE is shorter compared with other designs. The critical path delay of the proposed PE is reduced by 9% and 36% when compared to a Walter PE and Guo's bit-serial PE, respectively. Furthermore, the area requirement of the proposed PE is 16% smaller than that of a Walter PE. With a continuous data input, the proposed array can produce multiplication results at a rate of one per n+3 cycles with a latency of 3n + 6 cycles, where n is the bit size of the modulus. The proposed architecture includes the features of regularity, modularity, local interconnection, and unidirectional data flow. Accordingly, it is well suited to VLSI implementation.