The connection machine
Retargetable microcode synthesis
ACM Transactions on Programming Languages and Systems (TOPLAS)
VLSI array processors
A comparison-based instruction systolic array
Proceedings of the international workshop on Parallel algorithms & architectures
Instruction systolic array—tradeoff between flexibility and speed
Computer Systems Science and Engineering
Communicating sequential processes
Communications of the ACM
Guarded commands, nondeterminacy and formal derivation of programs
Communications of the ACM
Computational Aspects of VLSI
Introduction to Computer Architecture
Introduction to Computer Architecture
Paper: Program compression on the instruction systolic array
Parallel Computing
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The instruction systolic array (ISA) is a programmable parallel architecture suitable for VLSI implementation. This paper presents a generalization of the ISA, called the microprogrammed ISA, which uses simple microprogramming techniques. Microprogrammed ISAs use dynamic microcodes whose length and contents are tailor made to the current program to be executed, and this can be efficiently implemented in VLSI. Here, microprogramming has the novel advantage of extending the range of algorithms that can be implemented on a given ISA. In particular, microprogramming can extend an ISA's effective communication abilities. Also, the reduction of the program input bandwidth (and pinout) afforded by microprogramming is even more important on large-scale MIMD architectures, such as the ISA. This paper also presents a weakest precondition semantics for the (microprogrammed) ISA model, which provides a means for verifying microprogrammed ISA programs. The semantics is modeled at the micro level, and has potential in the optimization of the microcodes of ISA programs.