The connection machine
Memory requirements for balanced computer architectures
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
LISA: a parallel processing architecture
Proc. of the conference on algorithms and hardware for parallel processing on CONPAR 86
VLSI array processors
A comparison-based instruction systolic array
Proceedings of the international workshop on Parallel algorithms & architectures
The warp computer: Architecture, implementation, and performance
IEEE Transactions on Computers
Microprogramming instruction systolic arrays
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
Advanced Computer Design
Computer
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Large-scale mesh-connected networks need to be made flexibly and yet efficiently programmable. To meet this need, this paper describes various approaches for program compression for the Instruction Systolic Array (ISA), a mesh model well suited to large-scale VLSI implementation. The implementations of these approaches match the (systolic) mesh's suitability for VLSI, have a modest area overhead and can significantly improve the ISA's overall performance, reduce the ISA system's overall hardware costs and, in the case of microprogramming, even improve flexibility. These techniques can also be applied to the less flexible SIMD mesh and the more flexible MIMD mesh. However, since they mitigate the ISA's chief relative disadvantages over the SIMD mesh model, they considerably reduce the attractiveness of the SIMD mesh as a fine-grained mesh model.