VLSI array processors
A bit level systolic array for Walsh-Hadamard transforms
Signal Processing
Digital image processing
Hardware Implementation of Bluetooth Security
IEEE Pervasive Computing
Evolving Quantum Circuits Using Genetic Algorithm
EH '02 Proceedings of the 2002 NASA/DoD Conference on Evolvable Hardware (EH'02)
Design and Prototyping a Fast Hadamard Transformer for WCDMA
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
Hardware to Compute Walsh Coefficients
ISMVL '05 Proceedings of the 35th International Symposium on Multiple-Valued Logic
A DHT-based FFT/IFFT processor for VDSL transceivers
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
Accelerating colour space conversion on reconfigurable hardware
Image and Vision Computing
Scheduling multimedia services in a low-power MAC for wireless andmobile ATM networks
IEEE Transactions on Multimedia
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel split-radix fast algorithm for 2-D discrete Hartley transform
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Perceptually adaptive spread transform image watermarking scheme using Hadamard transform
Information Sciences: an International Journal
Accurate Area, Time and Power Models for FPGA-Based Implementations
Journal of Signal Processing Systems
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Fast Hadamard transform (FHT) belongs to the family of discrete orthogonal transforms and is used widely in image and signal processing applications. In this paper, a parameterizable and scalable architecture for FHT with time and area complexities of O(2(W + 1)) and O(2N2), respectively, has been proposed, where W and N are the word and vector lengths. A novel algorithmic transformation for the FHT based on sparse matrix factorization and distributed arithmetic (DA) principles has been presented. The architecture has been parallelized and pipelined in order to achieve high throughput rates. Efficient and optimized field-programmable gate array implementation of the proposed architecture that yield excellent performance metrics has been analyzed in detail. Additionally, a functional level power analysis and modeling methodology has been proposed to characterize the various power and energy metrics of the cores in terms of system parameters and design variables. The mathematical models that have been derived provide quick presilicon estimate of power and energy measures, allowing intelligent tradeoffs when incorporating the developed cores as subblocks in hardware-based image and video processing systems.