Processor array design with the use of genetic algorithm

Authors:
Piotr Ratuszniak
Affiliations:
Koszalin University of Technology, Koszalin, Poland
Venue:
LSSC'11 Proceedings of the 8th international conference on Large-Scale Scientific Computing
Year:
2011

Citing 4
Cited 0

VLSI array processors

VLSI array processors
A Method for Mapping DSP Algorithms into Application Specific Structures

EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Trend and Challenge on System-on-a-Chip Designs

Journal of Signal Processing Systems
BLAS Comparison on FPGA, CPU and GPU

ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper a method for processors arrays design dedicated to realization of specimen linear algebra algorithms in FPGA devices is presented. Within an allocation mapping process a genetic algorithm for information dependency graph projection is used and the runtime of the given algorithm is optimized. For larger input matrices, graph decomposition is used which allows the projection results to be obtained. The obtained projection results, with and without graph decomposition, for a specimen linear algebra algorithm are compared. Additionally, a parallel realization of the evolutionary algorithm for multicore processors is presented, which allows projection results to be obtained for larger input matrix sizes.