VLSI array processors
VLSI Architectures for multidimensional fourier transform processing
IEEE Transactions on Computers
IEEE Transactions on Computers
Parallel Processing: From Applications to Systems
Parallel Processing: From Applications to Systems
Systematic Approach and Software Tool for Systolic Design
CONPAR 94 - VAPP VI Proceedings of the Third Joint International Conference on Vector and Parallel Processing: Parallel Processing
Multi-dimensional systolic networks, for discrete fourier transform
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
| Hi-index | 0.00 |
In this chapter, the design of systolic array processors (SAPs) for computing multi-dimensional discrete Fourier transform (r-D DFT) is considered. We introduce two approaches of design: one uses the data For the first approach, we investigated three different computational schemes for designing SAPs for 2-D DFT. The systematic method guarantees to find optimal SAPs from a large solution space in terms of the number of processing elements and I/O channels, the processing time, topology, pipeline period, etc. This approach is difficult to extend to the 3-D case since the 6-D data dependency graph for the 3-D DFT cannot be reduced easily. Therefore, for the 3-D DFT we propose another approach: the dimensional splitting method. Using this method, computing of the r-D DFT with r ≥ 2 is done iteratively with each iteration handling the 1-D DFTs of different dimensions. Finally, an application of the proposed SAPs to the prime-factor DFT is presented.