VLSI array processors
Measuring the scalability of parallel computer systems
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Scalability of parallel machines
Communications of the ACM
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Computer Architecture: Parallelism,Scalability,Programmability
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In this paper we will present the results of mapping and simulating the B-Mode (echo), and Doppler (flow) algorithms in ultrasound processing onto 1D and 2D based architectures. A scaleable parallel architecture using commercial off the shelf DSP processors was simulated/evaluated for performance and cost feasibility to replace an existing dedicated hardware solution. The results showed that such an architecture was both feasible and cost effective.