VLSI array processors
Computer
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In this paper, a new approach for a memory-based VLSI realization of 1D Discrete Cosine Transform (1D-DCT), that significantly improve the previous designs, is presented. This approach is based on a new formulation of a prime-length DCT algorithm. It uses two half-length cyclic convolutions with the same form, which are such reformulated that multipliers can be efficiently replaced by small biport ROM's, and are computed in parallel. Using this approach, high structural regularity, low hardware cost of the PE's and average computation time, and low I/O cost can be obtained. So, the average computation time has been reduced to one half and the throughput has been doubled, as compared with, Thus, an efficient systolic array for DCT, which is well suited for VLSI realization, can be obtained. It possesses also a much lower control complexity, a simpler interconection structure, and a simpler hardware structure of the PE's, having thus a shorter cycle time. Moreover, it owns all the other outstanding features of the VLSI array proposed.