A programmable array processor architecture for flexible approximate string matching algorithms

  • Authors:

  • Panagiotis D. Michailidis;Konstantinos G. Margaritis

  • Affiliations:

  • Parallel and Distributed Processing Laboratory, Department of Applied Informatics, University of Macedonia, 156 Egnatia Street, P.O. Box 1591, 54006 Thessaloniki, Greece;Parallel and Distributed Processing Laboratory, Department of Applied Informatics, University of Macedonia, 156 Egnatia Street, P.O. Box 1591, 54006 Thessaloniki, Greece

  • Venue:
  • Journal of Parallel and Distributed Computing
  • Year:
  • 2007

Quantified Score

Hi-index 0.00

Visualization

Abstract

Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array processor architecture for a wide variety of approximate string matching algorithms to gain high performance at low cost. Further, we describe the architecture of the array and the architecture of the cell in detail in order to efficiently implement for both the preprocessing and searching phases of most string matching algorithms. Further, the architecture performs approximate string matching for complex patterns that contain don't care, complement and classes symbols. We also simulate and evaluate the proposed architecture on a field programmable gate array (FPGA) device using the JHDL tool for synthesis and the Xilinx Foundation tools for mapping, placement, and routing. Finally, our programmable implementation achieves about 8-340 times faster execution than a desktop computer with a Pentium 4 3.5GHz for all algorithms when the length of the pattern is 1024.