Kestrel: A Programmable Array for Sequence Analysis

Authors:
Jeffrey D. Hirschberg;Richard Hughey;Kevin Karplus;Don Speck
Affiliations:
-;-;-;-
Venue:
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Year:
1996

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Abstract

Kestrel is a programmable linear systolic array processor designed for sequence analysis. Among other features, Kestrel includes an 8-bit word, a single-cycle add-and-minimize instruction, and efficient communication using Systolic Shared Registers. This paper describes Kestrel's functional units in detail, and examines each of their effects on system performance. With prototypes currently in the works, we expect to complete a full Kestrel array, with between 512 and 1024 processing elements, in 1997.