Massively Parallel Solutions for Molecular Sequence Analysis
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Run-Time Parameterizable Cores
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Unexpected means of protocol inference
Proceedings of the 6th ACM SIGCOMM conference on Internet measurement
Accelerator design for protein sequence HMM search
Proceedings of the 20th annual international conference on Supercomputing
A programmable array processor architecture for flexible approximate string matching algorithms
Journal of Parallel and Distributed Computing
Implementation of the Smith-Waterman algorithm on a reconfigurable supercomputing platform
HPRCTA '07 Proceedings of the 1st international workshop on High-performance reconfigurable computing technology and applications: held in conjunction with SC07
Processor array architectures for flexible approximate string matching
Journal of Systems Architecture: the EUROMICRO Journal
DNA Physical Mapping on a Reconfigurable Platform
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
The new SIMD Implementation of the Smith-Waterman Algorithm on Cell Microprocessor
Fundamenta Informaticae
Hardware Acceleration of HMMER on FPGAs
Journal of Signal Processing Systems
Reducing storage requirements in accelerating algorithm of global BioSequence alignment on FPGA
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Glacier: a query-to-hardware compiler
Proceedings of the 2010 ACM SIGMOD International Conference on Management of data
Bio-sequence database scanning on a GPU
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Some initial results on hardware BLAST acceleration with a reconfigurable architecture
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
FPGA based architecture for DNA sequence comparison and database search
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A highly parameterized and efficient FPGA-based skeleton for pairwise biological sequence alignment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware designs for local alignment of protein sequences
ISCIS'06 Proceedings of the 21st international conference on Computer and Information Sciences
Microprocessors & Microsystems
Biological sequence analysis with hidden markov models on an FPGA
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
High performance biological pairwise sequence alignment: FPGA versus GPU versus cell BE versus GPP
International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
Optimization schemes and performance evaluation of Smith–Waterman algorithm on CPU, GPU and FPGA
Concurrency and Computation: Practice & Experience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Protein sequences with unknown functionality are often compared to a set of known sequences to detect functional similarities. Efficient dynamic-programming algorithms exist for solving this problem, however current solutions still require significant scan times. These scan time requirements are likely to become even more severe due to exponential database growth. In this paper we present a new approach to bio-sequence database scanning using re-configurable FPGA-based hardware platforms to gain high performance at low cost. Efficient mappings of the Smith-Waterman algorithm using fine-grained parallel processing elements (PEs) that are tailored towards the parameters of a query have been designed. We use customization opportunities available at run-time to dynamically hyper customize the systolic array to make better use of available resource. Our FPGA implementation achieves a speedup of approximately 170 for linear gap penalties and 125 for affine gap penalties as compared to a standard desktop computing platform. We show how hyper-customization at run-time can be used to further improve the performance.