FPL Implementation of Systolic Sequence Alignment
Selected papers from the Second International Workshop on Field-Programmable Logic and Applications, Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Assisting Network Intrusion Detection with Reconfigurable Hardware
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Run-Time Reconfigurable System for Gene-Sequence Searching
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Hyper customized processors for bio-sequence database scanning on FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
RC-BLAST: Towards a Portable, Cost-Effective Open Source Hardware Implementation
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 7 - Volume 08
Fast Regular Expression Matching Using FPGAs
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A General Reconfigurable Architecture for the BLAST Algorithm
Journal of VLSI Signal Processing Systems
Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Some initial results on hardware BLAST acceleration with a reconfigurable architecture
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Reconfigurable accelerator for the word-matching stage of BLASTN
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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DNA sequence comparison is a computationally intensive problem, known widely since the competition for human DNA decryption. Database search for DNA sequence comparison is of great value to computational biologists. Several algorithms have been developed and implemented to solve this problem efficiently, but from a user base point of view the BLAST algorithm is the most widely used one. In this paper we present a new architecture for the BLAST algorithm. The new architecture was fully designed, placed and routed. The post place-and-route cycle-accurate simulation, accounting for the I/O, shows a better performance than a cluster of workstations running highly optimized code over identical datasets. The new architecture and detailed performance results are presented in this paper.