Hyper customized processors for bio-sequence database scanning on FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Sequence Alignment with Traceback on Reconfigurable Hardware
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Acceleration of the Smith-Waterman algorithm using single and multiple graphics processors
Journal of Computational Physics
A Parallel Programming Framework for Multi-core DNA Sequence Alignment
CISIS '10 Proceedings of the 2010 International Conference on Complex, Intelligent and Software Intensive Systems
A highly parameterized and efficient FPGA-based skeleton for pairwise biological sequence alignment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
A flexible hardware architecture that implements a set of new and efficient techniques to significantly reduce the computational requirements of the commonly used Smith-Waterman sequence alignment algorithm is presented. Such innovative techniques use information gathered by the hardware accelerator during the computation of the alignment scores to constrain the size of the subsequence that has to be post-processed in the traceback phase using a general purpose processor (GPP). Moreover, the proposed structure is also capable of computing the n-best local alignments according to the Waterman-Eggert algorithm, becoming the first hardware architecture that is able to simultaneously evaluate the n-best alignments of a given sequence pair, by incorporating a set of ordering units that work in parallel with the systolic array. A complete alignment system was developed and implemented in a Virtex-4 FPGA, by integrating the proposed accelerator architecture with a Leon3 GPP. The obtained experimental results demonstrate that the proposed system is flexible and allows the alignment of large sequences in memory constrained systems. As an example, a speedup of 17 was obtained with the conceived system when compared with a regular implementation of the LALIGN35 program running on an Intel Core2 Duo processor running at a 40× higher frequency.