High performance biological pairwise sequence alignment: FPGA versus GPU versus cell BE versus GPP

Authors:
Khaled Benkrid;Ali Akoglu;Cheng Ling;Yang Song;Ying Liu;Xiang Tian
Affiliations:
Institute of Integrated Systems, School of Engineering, The University of Edinburgh, Edinburgh, UK;Electrical and Computer Engineering Department, The University of Arizona, Tucson, AZ;Institute of Integrated Systems, School of Engineering, The University of Edinburgh, Edinburgh, UK;Institute of Integrated Systems, School of Engineering, The University of Edinburgh, Edinburgh, UK;Institute of Integrated Systems, School of Engineering, The University of Edinburgh, Edinburgh, UK;Institute of Integrated Systems, School of Engineering, The University of Edinburgh, Edinburgh, UK
Venue:
International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
Year:
2012

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Abstract

This paper explores the pros and cons of reconfigurable computing in the form of FPGAs for high performance efficient computing. In particular, the paper presents the results of a comparative study between three different acceleration technologies, namely, Field Programmable Gate Arrays (FPGAs), Graphics Processor Units (GPUs), and IBM's Cell Broadband Engine (Cell BE), in the design and implementation of the widely-used Smith-Waterman pairwise sequence alignment algorithm, with general purpose processors as a base reference implementation. Comparison criteria include speed, energy consumption, and purchase and development costs. The study shows that FPGAs largely outperform all other implementation platforms on performance per watt criterion and perform better than all other platforms on performance per dollar criterion, although by a much smaller margin. Cell BE and GPU come second and third, respectively, on both performance per watt and performance per dollar criteria. In general, in order to outperform other technologies on performance per dollar criterion (using currently available hardware and development tools), FPGAs need to achieve at least two orders of magnitude speed-up compared to general-purpose processors and one order of magnitude speed-up compared to domain-specific technologies such as GPUs.