VLSI array processors
Digital Signal Processing with Field Programmable Gate Arrays with Cdrom
Digital Signal Processing with Field Programmable Gate Arrays with Cdrom
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In this paper, we propose a novel Hardware/Software (HW/SW) co-design approach for near real time implementation of high-resolution reconstruction of remote sensing (RS) imagery using an efficient network of systolic arrays (NSA). Such proposed NSA technique is based on a Field Programmable Gate Array (FPGA) and implements the image enhancement/reconstruction tasks of the intelligent descriptive experiment design regularization (DEDR) methodology in an efficient concurrent processing architecture that meets the (near) real time imaging systems requirements in spite of conventional computations. Finally, the results of the HW/SW co-design implementation in a Xilinx Virtex-4 XC4VSX35-10ff668 for the reconstruction of real world RS images are reported and discussed.