VLSI array processors
Algorithms on strings, trees, and sequences: computer science and computational biology
Algorithms on strings, trees, and sequences: computer science and computational biology
Term rewriting and all that
Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Theoretical Computer Science - Rewriting logic and its applications
ELAN from a rewriting logic point of view
Theoretical Computer Science - Rewriting logic and its applications
Maude: specification and programming in rewriting logic
Theoretical Computer Science - Rewriting logic and its applications
Logical foundations of cafeOBJ
Theoretical Computer Science - Rewriting logic and its applications
Mechanizing Verification of Arithmetic Circuits: SRT Division
Proceedings of the 17th Conference on Foundations of Software Technology and Theoretical Computer Science
Hardware Synthesis from Term Rewriting Systems
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Configware and morphware going mainstream
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computer Vision and Image Understanding
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Systolic arrays provide a large amount of parallelism. However, their applicability is restricted to a small set of computational problems due to their lack of flexibility. This limitation can be circumvented by using reconfigurable systolic arrays, where the node interconnections and operations can be redefined even at run time. In this context, several alternative systolic architectures can be explored and powerful tools are needed to model and evaluate them. We show how well-known rewriting-logic environments could be used to quickly model and simulate complex application specific digital systems speeding-up its subsequent prototyping. We show how to use rewriting-logic to model and evaluate reconfigurable systolic architectures which are applied to the efficient treatment of several dynamic programming methods for resolving well-known problems such as global and local sequence alignment (Smith-Waterman algorithm), approximate string matching and computation of the longest common subsequence. A VHDL description of the conceived architecture was implemented from the rewriting-logic based abstract models and synthesized over an FPGA of the APEX family.