Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic

Authors:
Mauricio Ayala-Rincón;Rodrigo B. Nogueira;Carlos H. Llanos;Ricardo P. Jacobi;Reiner W. Hartenstein
Affiliations:
-;-;-;-;-
Venue:
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Year:
2003

Citing 0
Cited 2

Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic

SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic

ACM Transactions on Design Automation of Electronic Systems (TODAES)

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Abstract

The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectures, the choice of an efficient architecture and reconfiguration scheme for a given application is a complex task. Tools for exploration of design alternatives at higher abstraction levels are needed. This paper describes the modeling and simulation of a dynamically reconfigurable hardware implementation of the Fast Fourier Transform 驴 FFT using rewriting-logic. Itis shown that rewriting-logic can be used as a framework for fast design space exploration, providing a quick evaluation of different reconfigurable solutions.