Design of efficient architectures for 1-D and 2-D DLMS adaptive filters

Authors:
K. R. Santha;V. Vaidehi
Affiliations:
Department of Electrical and Electronics Engineering, Sri Venkateswara College of Engineering, Chennai;Department of Electronics, Madras Institute of Technology, Chennai
Venue:
Integration, the VLSI Journal
Year:
2007

Citing 6
Cited 0

VLSI array processors

VLSI array processors
Digital integrated circuits: a design perspective

Digital integrated circuits: a design perspective
Digital Signal Processing Handbook

Digital Signal Processing Handbook
Corrections to `The LMS algorithm with delayed coefficientadaptation'

IEEE Transactions on Signal Processing
A systolic array realization of an LMS adaptive filter and theeffects of delayed adaptation

IEEE Transactions on Signal Processing
A pipelined LMS adaptive FIR filter architecture without adaptationdelay

IEEE Transactions on Signal Processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a design of systolic array architectures for 1-D and 2-D finite impulse response adaptive filters. The design is based on the delayed least mean squares algorithm (DLMS). Two designs have been proposed and their performance is analyzed in terms of speed up, adaptation delay and throughput. The second realization results in a lowest critical period equal to one multiply operation time and a higher throughput. Unlike the existing architectures the adaptation delay of this design is independent of the filter length and has a higher speedup. It is shown that the convergence performance of this design is in par with the conventional LMS algorithm.