Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modern
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Pipelining the adaptive decision feedback equalizer with zero latency
Signal Processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of efficient architectures for 1-D and 2-D DLMS adaptive filters
Integration, the VLSI Journal
| Hi-index | 35.68 |
Past methods for mapping the least-mean-square (LMS) adaptive finite-impulse-response (FIR) filter onto parallel and pipelined architectures either introduce delays in the coefficient updates or have excessive hardware requirements. We describe a hardware-efficient pipelined architecture for the LMS adaptive FIR filter that produces the same output and error signals as would be produced by the standard LMS adaptive filter architecture without adaptation delays. Unlike existing architectures for delayless LMS adaptation, the new architecture's throughput is independent of the filter length