Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers

Authors:
Lok-Kee Ting;Roger Woods;Colin. F. N. Cowan
Affiliations:
Intel Microelectronics, Bayan Lepas Fee Industrial Zone Phase 3, 11900 Penang, Malaysia and The Queen's University of Belfast, BT9 5AH Belfast, N. Ireland;School of Electrical and Electronic Engineering, The Queen's University of Belfast, BT9 5AH Belfast, N. Ireland;School of Electrical and Electronic Engineering, The Queen's University of Belfast, BT9 5AH Belfast, N. Ireland
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

Citing 2
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Abstract

High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in an increased output latency when used in the LMS recursive system. Therefore, the major challenge is to maintain a low latency output whilst increasing the pipeline stage in the filter for higher speeds. Using the delayed LMS (DLMS) algorithm, fine-grained pipelined FPGA implementations using both the direct form (DF) and the transposed form (TF) are considered and compared. It is shown that the direct form LMS filter utilizes the FPGA resources more efficiently thereby allowing a 120 MHz sampling rate.