Retiming of synchronous circuits with variable topology

Authors:
S. Simon;R. Bucher;J. A. Nossek
Affiliations:
-;-;-
Venue:
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Year:
1995

Citing 5
Cited 0

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Performance optimization of sequential circuits by eliminating retiming bottlenecks

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Computational Aspects of VLSI

Computational Aspects of VLSI

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Abstract

Generally, circuit design leads to a trade-off scenario between speed and various parameters like power dissipation, AT complexity, re-use of already existing cells, design time, etc. To deal with this trade-off the interaction between retiming and the selection of combinational elements from a set of cells with these different parameters is considered here. Additionally, modifications of the circuit graph concerning the interconnections, e.g. due to associativity of the underlying algorithm, lead to a parameterized topology. The algorithm presented an this paper combines all three, retiming, the selection of specific cells and the choice of an appropriate topology in one optimization step.