Regular interactive algorithms and their implementations on processor arrays
Regular interactive algorithms and their implementations on processor arrays
VLSI array processors
New approach to parallel systolic algorithm implementations—RLSL example
Signal Processing
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Certain real-time applications (e.g. signal filtering and processing in a digital communication system) require the use of a special massively parallel computing structure, called the systolic array structure, to achieve acceptable performance. To implement an algorithm this way, we need a mapping procedure to map a set of equations, which describe the algorithm, to the systolic array. This mapping consists of scheduling (i.e. time mapping, mapping of each DG node to a particular time instant) and space mapping (mapping of each DG node to a systolic array cell). In the paper we propose a new approach to scheduling of complicated algorithms (that are described by a set of equations, fulfilling the requirement of regularity, i.e. constant dependence vectors). It takes into account the exact computational requirements of the basic arithmetic operations used, and yields near optimal scheduling from the viewpoint of execution speed of the resulting implementation.