VLSI systolic binary tree-searched vector quantizer for image compression

  • Authors:

  • Wai-Chi Fang;Chi-Yung Chang;Bing J. Sheu;Oscal T.-C. Chen;John C. Curlander

  • Affiliations:

  • Department of Electrical Engineering, University of Southern California, Signal and Image Processing Institute, Los Angeles, CA;Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA;Department of Electrical Engineering, University of Southern California, Los Angeles, CA;Department of Electrical Engineering, University of Southern California, Los Angeles, CA;Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 1994

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Abstract

A high-speed image compression VLSI processor based on the systolic architecture of difference-codebook binary tree-searched vector quantization has been developed to meet the increasing demands on large-volume data communication and storage requirements. Simulation results show that this design is applicable to many types of image data and capable of producing good reconstructed data quality at high compression ratios. Various design aspects of the binary tree-searched vector quantizer including the algorithm, architecture, and detailed functional design are thoroughly investigated for VLSI implementation. An 8-level difference-codebook binary tree-searched vector quantizer can be implemented on a custom VLSI chip that includes a systolic array of eight identical processors and a hierarchical memory of eight subcodebook memory banks. The total transistor count is about 300 OOO and the die size is about 8.67 × 7.72 mm2 in a 1.0 mm CMOS technology. The throughput rate of this high-speed VLSI compression system is approximately 25 M pixels per second and its equivalent computation power is 600 million instructions per second.