Reconfigurable architecture of systolic array processors for remote sensing applications

  • Authors:

  • A. Castillo Atoche;D. Torres Roman;Y. Shkvarko

  • Affiliations:

  • Department of Telecomunications, CINVESTAV del IPN, Unidad Guadalajara, Zapopan, Jalisco, Mexico and Department of Mechatronics, Universidad Autónoma de Yucatán, Mérida, Yucatá ...;Department of Telecomunications, CINVESTAV del IPN, Unidad Guadalajara, Zapopan, Jalisco, Mexico;Department of Telecomunications, CINVESTAV del IPN, Unidad Guadalajara, Zapopan, Jalisco, Mexico

  • Venue:
  • SSIP '09/MIV'09 Proceedings of the 9th WSEAS international conference on signal, speech and image processing, and 9th WSEAS international conference on Multimedia, internet & video technologies
  • Year:
  • 2009

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Abstract

In this paper, we propose a reconfigurable architecture of systolic array (SA) processors for near real time implementation of high-resolution reconstruction of remote sensing (RS) imagery. The proposed design is based on a Field Programmable Gate Array (FPGA) and performs the image enhancement/reconstruction tasks in an efficient reconfigurable processing architecture mode that involves the array processors aimed to meet the (near) real time imaging systems requirements in spite of conventional computations. In particular, the selected reconstructive signal processing techniques (i.e. matrix-matrix and matrix-vector multiplication) are implemented employing the proposed reconfigurable architecture with the objective to decrease the computational load of the large-scale RS image enhancement tasks via employing the Hardware/Software Co-Design paradigm.