Minimizing the number of delay buffers in the synchronization of pipelined systems

Authors:
X. Hu;R. G. Harber;S. C. Bass
Affiliations:
General Motons Research Laboratories, Warren, MI;Hewlett-Packard Co., Fort Collins, CO;Geo. Mason University and MITRE Corp., McLean, VA
Venue:
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Year:
1991

VLSI array processors

VLSI array processors
Combinatorial optimization: algorithms and complexity

Combinatorial optimization: algorithms and complexity
A faster strongly polynomial minimum cost flow algorithm

STOC '88 Proceedings of the twentieth annual ACM symposium on Theory of computing
The Design and Analysis of Computer Algorithms

The Design and Analysis of Computer Algorithms
A silicon compiler for dedicated mathematical systems based on cordic arithmetic processors

A silicon compiler for dedicated mathematical systems based on cordic arithmetic processors

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